1. Field
Example embodiments relate to apparatuses and/or methods that may program data in memory cells of memory devices. Also, example embodiments relate to multi-bit programming apparatuses and/or methods that may program data in multi-level cells (MLCs) or multi-bit cells (MBCs) of MLC memory devices.
2. Description of Related Art
A single-level cell (SLC) memory device may store one bit of data in a single memory cell. The SLC memory may be referred to as a single-bit cell (SBC) memory. The SLC memory may store and read data of one bit at a voltage level included in two distributions that may be divided by a threshold voltage level programmed in a memory cell. Due to a fine electrical characteristic difference between SLC memories, the programmed threshold voltage level may have the distribution within a predetermined range. For example, when a voltage level read from the memory cell is greater than 0.5V and less than 1.5V, it may be determined that the data stored in the memory cell has a logic value of “0”. When the voltage level read from the memory cell is greater than 2.5V and less than 3.5V, it may be determined that the data stored in the memory cell has a logic value of “1”. The data stored in the memory cell may be classified depending on the difference between cell currents and/or cell voltages during the reading operations.
Meanwhile, a multi-level cell (MLC) memory device that can store data of two or more bits in a single memory cell has been proposed in response to a need for higher integration of memory. The MLC memory device may also be referred to as a multi-bit cell (MBC) memory. However, as the number of bits stored in the single memory cell increases, reliability may deteriorate and the read-failure rate may increase. To store ‘m’ bits in a single memory cell, 2m voltage level distributions may be required. However, since the voltage window for a memory cell may be limited, the difference in threshold voltage between adjacent bits may decrease as ‘m’ increases, which may cause the read-failure rate to increase. For this reason, it may be difficult to improve storage density using a MLC memory device.
With the current increase in the utilization of the MLC memory device, error correction codes or error control codes (ECC) that can detect an error during data storing and reading operations and correct the detected error is being more widely used.
Disclosed herein are new multi-level (multi-bit) programming apparatuses and methods for reducing the hardware complexity when embodying ECC hardware.